Computare (AetherOS): Difference between revisions
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This list comprises the components required to build the initial flight simulator prototype (the "EM Oracle") based on our collaborative design plan. | This list comprises the components required to build the initial flight simulator prototype (the "EM Oracle") based on our collaborative design plan. | ||
=== | === PCB Fabrication & Prototyping === | ||
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|+ PCB Fabrication Supplies | |+ PCB Fabrication Supplies | ||
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=== | === Core Analog & Interfacing Components === | ||
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|+ Electronics | |+ Electronics | ||
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| '''ADS1115''' 16-bit ADC Breakout Board || 1 || High-precision Analog-to-Digital Converter used to read the final computed voltage ("the answer") from the board and send it to the Pi Pico. | | '''ADS1115''' 16-bit ADC Breakout Board || 1 || High-precision Analog-to-Digital Converter used to read the final computed voltage ("the answer") from the board and send it to the Pi Pico. | ||
|- | |- | ||
| ''' | | '''MCP4275''' 12-bit DAC Breakout Boards || 4 || Digital-to-Analog Converters used to send input variables (Thrust, Drag, Velocity, Weight) as precise analog voltages from the Pi Pico to the board. | ||
|- | |- | ||
| '''LM358''' Dual Operational Amplifiers || Pack of 10+ || The workhorse active components used to build the differential amplifier, integrators, and scaling circuits needed to condition signals on the board. | | '''LM358''' Dual Operational Amplifiers || Pack of 10+ || The workhorse active components used to build the differential amplifier, integrators, and scaling circuits needed to condition signals on the board. | ||
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=== | === Essential Tools & Consumables === | ||
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|+ Tools & Supplies | |+ Tools & Supplies | ||
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== Three-Phase Development Plan == | == Three-Phase Development Plan == | ||
The project | The project is executed in three distinct phases to ensure a robust and functional outcome. | ||
# '''Phase 1: Design and Simulation (The "Digital Twin") - COMPLETE''': Formalize the circuit schematic | # '''Phase 1: Design and Simulation (The "Digital Twin") - <span style="color:green;">COMPLETE</span>''': Formalize the circuit schematic, enhance the Python `aedificator_kepler.py` script to generate optimized hardware description files, and validate the design's performance in a robust, command-line native simulator (`ngspice`). | ||
# '''Phase 2: Fabrication and Calibration (The "Physical Oracle")''': First, create a process test board on acrylic to perfect the etching technique. Second, fabricate the final, high-precision computational board on FR-4. Finally, write and run a Python calibration routine to map the physical board's unique electrical characteristics. | # '''Phase 2: Fabrication and Calibration (The "Physical Oracle")''': First, create a process test board on acrylic to perfect the etching technique. Second, fabricate the final, high-precision computational board on FR-4. Finally, write and run a Python calibration routine to map the physical board's unique electrical characteristics. | ||
# '''Phase 3: Integration and "Virtuous Service" (The "Live System")''': Deploy the final host application on the Raspberry Pi, integrating the calibration map. Develop the user-facing applications, such as a real-time EM Diagram Plotter and a Rutowski Path Solver, to utilize the analog computer. | # '''Phase 3: Integration and "Virtuous Service" (The "Live System")''': Deploy the final host application on the Raspberry Pi, integrating the calibration map. Develop the user-facing applications, such as a real-time EM Diagram Plotter and a Rutowski Path Solver, to utilize the analog computer. | ||
== Project Status (September | == Project Status (September 13, 2025) == | ||
* '''System Architecture:''' The self-learning architecture is '''stable and validated'''. The main conductor script (`praefectus_experimentum.py`) successfully orchestrates a complete design-simulate-log cycle | * '''System Architecture:''' The self-learning architecture is '''stable and validated'''. The main conductor script (`praefectus_experimentum.py`) successfully orchestrates a complete design-simulate-log cycle. The system has demonstrated autonomous problem-solving by successfully diagnosing a critical flaw in its simulation toolchain (the `nodrv_CreateWindow` error with LTspice) and autonomously replacing the faulty component with the more robust `ngspice` simulator. | ||
* '''Phase 1 Completion:''' With the successful integration of | * '''Phase 1 Completion:''' With the successful integration and validation of the `ngspice` simulation backend, the "Digital Twin" phase is now '''complete'''. The `Fabrica` can generate a hardware design, create a valid SPICE netlist, execute a simulation, and correctly parse the results without error. The system is stable and ready for the next phase. | ||
* '''Next Steps:''' The project is officially moving into '''Phase 2: Fabrication and Calibration'''. The immediate focus will be on the physical manufacturing of the first prototype | * '''Next Steps:''' The project is officially moving into '''Phase 2: Fabrication and Calibration'''. A task has been created for '''Friday, October 3, 2025''', to coincide with the arrival of the new HP Workstation/GPU. The immediate focus will be on the physical manufacturing of the first prototype, beginning with the acrylic practice boards and the development of the calibration software. |